Programmable array logic

ABSTRACT

A programmable array logic includes a plurality of first signal lines, a plurality of second signal lines coupled to input terminals of a plurality of programmable AND gates, a plurality of first control units coupled to the first signal lines and second signal lines, a plurality of third signal lines coupled to output terminals of the programmable AND gates, a plurality of fourth signal lines coupled to input terminals of a plurality of programmable OR gates, and a plurality of second control units coupled to the third signal lines and the fourth signal lines. Each of the first control units has at least a first resistive memory for setting voltage level relationship between the first signal lines and the second signal lines. Each of second control units has a second resistive memory for setting voltage level relationship between the third signal lines and the fourth signal lines.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan applicationserial no. 107126723, filed on Aug. 1, 2018. The entirety of theabove-mentioned patent application is hereby incorporated by referenceherein and made a part of this specification.

BACKGROUND

Technical Field

The invention relates to a programmable circuit, and more particularlyto a programmable array logic.

Description of Related Art

Programmable array logic (PAL) is a programmable logic device that canimplement a combinational logic circuit. The programmable array logichas a set of programmable AND gates and a set of programmable OR gatesconfigured to allow a logic signal output to be enabled when theconditions are met. Since the programmable array logic is easier toprogram, the programmable array logic has been widely used. However, inthe field of programming, the flexibility, performance and cost aresteady trends, therefore, there is still a need for a newer circuitdesign.

SUMMARY

The invention provides a programmable array logic, which can set therelationship between the voltage levels of the signal lines by settingand resetting the resistive memory, so as to improve the flexibility andperformance of the use without compromising hardware cost.

In an embodiment of the invention, the programmable array logic includesa plurality of programmable AND gates, a plurality of first signallines, a plurality of second signal lines, a plurality of first controlunits, a plurality of programmable OR gates, a plurality of third signallines, a plurality of fourth signal lines, and a plurality of secondcontrol units. These second signal lines are respectively coupled to theinput terminals of the programmable AND gates. The first control unit iscoupled to the corresponding first signal line and the correspondingsecond signal line, and each first control unit has at least a firstresistive memory, and the first resistive memory is configured toisolate the coupled first signal line from the coupled second signalline, and set a relationship between a voltage level of thecorresponding first signal line and a voltage level of the correspondingsecond signal line. The third signal lines are respectively coupled tothe output terminals of the programmable AND gates, and the fourthsignal lines are respectively coupled to the input terminals of theprogrammable OR gates. The second control unit is coupled to thecorresponding third signal line and the corresponding fourth signalline, and each second control unit has a second resistive memory, thesecond resistive memory is configured to isolate the coupled thirdsignal line from the coupled fourth signal line, and set a relationshipbetween a voltage level of the corresponding third signal line and avoltage level of the corresponding fourth signal line.

Based on the above, the programmable array logic of the embodiment ofthe invention can set the relationship between the voltage levels of thefirst and second signal lines according to the information stored in thefirst resistive memory, and set the relationship between the voltagelevels of the third and fourth signal lines according to the informationstored in the second resistive memory. As a result, the flexibility andperformance of the use can be improved without compromising the hardwarecost.

The above described features and advantages of the invention will bemore apparent from the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a system of programmable array logicaccording to an embodiment of the invention.

FIG. 2 is a schematic diagram of a circuit of a first control unitaccording to an embodiment of the invention.

FIG. 3 is a schematic diagram of a circuit of a first control unitaccording to an embodiment of the invention.

FIG. 4 is a schematic diagram of a circuit of a second control unitaccording to an embodiment of the invention.

DESCRIPTION OF THE EMBODIMENTS

FIG. 1 is a schematic diagram of a system of programmable array logicaccording to an embodiment of the invention. Referring to FIG. 1, in theembodiment, a programmable array logic 100 includes aninverting/non-inverting block 110, a wire-AND logic array 120, aplurality of programmable AND gates (e.g., PA_1˜PA_8), a wire-OR logicarray 130, and a plurality of programmable OR gates (e.g., PO_1˜PO_4).The amount of the programmable AND gates (e.g., PA_1˜PA_8) andprogrammable OR gates (e.g., PO_1˜PO_4) used are for illustrativepurposes, the embodiments of the invention is not limited thereto.

The inverting/non-inverting block 110 receives a plurality of input bits(e.g., I1, I2, and I4) to respectively provide the input bits (e.g., I1,I2, and I4) and inverted input bits (e.g., I1 b, I2 b and I4 b). Indetail, the inverting/non-inverting block 110 can include a plurality ofinverters (e.g., INT1˜INT3) that respectively receive the input bits,(e.g., I1, I2, and I4) to respectively provide the inverted input bits(e.g., I1 b, I2 b, and I4 b), and the input bits (e.g., I1, I2, and I4)are bypassed from input terminals of the inverting/non-inverting block110 to output terminals of the inverting/non-inverting block 110 throughwires. Thereby, the inverting/non-inverting block 110 can provide theinput bits (e.g., I1, I2, and I4) and the respective inverted input bits(e.g., I1 b, I2 b, and I4 b).

The wire-AND logic array 120 includes a plurality of first signal lines(e.g., 121_1˜121_6), a plurality of second signal lines (e.g.,123_1˜123_8), and a plurality of first control units CU1. One end of thefirst signal lines (e.g., 121_1˜121_6) is coupled to theinverting/non-invertng block 110 to receive the input bits (e.g., I1,I2, and I4) and the inverted input bits (e.g., I1 b, I2 b, and I4 b).Moreover, each of the first signal lines (e.g., 121_1˜121_6) receives,foexample, a corresponding input bit (e.g., one of the input bits I1,I2, and I4) or a corresponding inverted input bit (e.g., one of theinverted input bits I1 b, I2 b, and I4 b).

The second signal lines (e.g., 123_˜123_8) are intersected with thefirst signal lines (e.g., 121_1˜121_6) and are respectively coupled toinput terminals of the programmable AND gates (e.g., PA_1˜PA_8). Thefirst control units CU1 are disposed at intersection of the first signallines (e.g., 121_1˜121_6) and the second signal lines (e.g.,123_1˜123_8), and are respectively coupled to the corresponding firstsignal line (e.g., one of the first signal lines 121_1˜121_6) and thecorresponding second signal line (e.g., one of the second signal lines123_1˜123_8). Each first control unit CU1 has at least a first resistivememory RX1, wherein the first resistive memory RX1 is configured toisolate a first signal line (e.g., one of the first signal line121_1˜121_6) coupled thereto from a second signal line (e.g., one of thefirst signal line 123_1˜123_8) coupled thereto, that is, the firstsignal line (e.g., one of the first signal lines 121_1˜121_6) is notconducted to the second signal line (e.g., one of the second signallines 123_1˜123_8) through first resistive memory RX1 for any time.Moreover, the first resistive memory RX1 sets a relationship of avoltage level of the corresponding (coupled) first signal line (e.g.,one of the first signal lines 121_1˜121_6) and the corresponding(coupled) second signal line (e.g., one of the second signal lines123_1˜123_8) according to a stored bit information.

The wire-OR logic array 130 includes a plurality of third signal lines(e.g., 131_1˜131_8), a plurality of fourth signal lines (e.g.,133_1˜133_6), and a plurality of second control units CU2. The thirdsignal lines (e.g., 131_1˜131_8) are coupled to output terminals of theprogrammable AND gates (e.g., PA_1˜PA_8), and the fourth signal lines(e.g., 133_1˜133-4) are coupled to input terminals of the programmableOR gates (e.g., PO_1˜PO_4). In addition, the third signal lines (e.g.,131_1˜131_8) and the fourth signal lines (e.g., 133_1˜133_4) areintersected with each other. The programmable OR gates (e.g., PO_1˜PO_4)provides a plurality of output bits (e.g., F1, F2, F3, and F4).

The second control units CU2 are disposed at intersection of the thirdsignal lines (e.g., 131_1˜131_8) and the fourth signal lines (e.g.,133_1˜133_4), and are respectively coupled to the corresponding thirdsignal line (e.g., one of the third signal lines 131_1˜131_8) and thecorresponding fourth signal line (e.g., one of the fourth signal lines133_1˜133_4). Each second control unit CU2 has a second resistive memoryRX2, wherein the second resistive memory RX2 is configured to isolate athird signal line (e.g., one of third first signal lines 131_1˜131_8)coupled thereto from a fourth signal line (e.g., one of the fourthsignal lines 133_1˜133_4) coupled thereto, that is, the third signalline (e.g., one of the third signal lines 131_1˜131_8) is not conductedto the fourth signal line (e.g., one of the fourth signal lines133_1˜133_4) through the second resistive memory RX2 for any time. Thesecond resistive memory RX2 sets a relationship of a voltage level ofthe corresponding (coupled) third signal line (e.g., one of the thirdsignal lines 131_1˜131_8) and the corresponding (coupled) fourth signalline (e.g., one of the fourth signal lines 133_1˜133_4 according to thestored bit information.

According to the above, since the first resistive memory RX1 and thesecond resistive memory RX2 can be set and reset repeatedly, that is,the relationship between the voltage levels of the first signal line(e.g., one of the first signal lines 121_1˜121_6 and the second signalline (e.g., one of the second signal lines 123_1˜123_8), and therelationship between the voltage levels of the third signal line (e.g.,one of the third signal lines 131_1˜131_8) and the fourth signal line(e.g., one of fourth first signal lines 133_1˜133_4) can be resetrepeatedly, so that the flexibility and performance of the programmablearray logic 100 can be improved and the cost of use can also be reduced.

Among them, the amount of the first signal lines (e.g., 121_1˜121_6),the second signal lines (e.g., 123_1˜123_8), the third signal lines(e.g., 131_1˜131_8), and the fourth signal lines (e.g., 133_1˜133_4)used are for illustrative purposes, the embodiment of the invention isnot limited thereto.

FIG. 2 is a schematic diagram of a circuit of a first control unitaccording to an embodiment of the invention. Please refer to FIG. 1 andFIG. 2, wherein same or similar reference numerals are used for same orsimilar parts. In this embodiment, each first control unit CU1 includesa resistive memory RX11 (corresponding to the first resistive memory), aresistive memory RX12 (corresponding to a third resistive memory), aninverter INT11 (corresponding to the first inverter), transistors M13and M14 (corresponding to a first switch and a second switch). Theresistive memory RX11 includes a transistor M11 and an impedance elementR11, and the resistive memory RX12 includes a transistor M12 and animpedance element R12.

A first terminal of the transistor M11 (corresponding to a firstterminal of the first resistive memory) receives a first control voltageVC1, a control terminal of the transistor M11 (corresponding to acontrol terminal of the first resistive memory) is coupled to acorresponding first signal line 121, a second terminal of the transistorM11 is coupled to an anode of the impedance element R11. A cathode ofthe impedance element R11 (corresponding to a second terminal of thefirst resistive memory) receives a first line bias voltage VB1, a firstterminal of the transistor M12 (corresponding to a first terminal of thethird resistive memory) receives a second control voltage VC2, and acontrol terminal of the transistor M12 (corresponding to a controlterminal of the third resistive memory) is coupled to the correspondingfirst signal line 121, a second terminal of the transistor M12 iscoupled to an anode of the impedance element R12. A cathode of theimpedance element R12 (corresponding to a second terminal of the thirdresistive memory) receives the first line bias voltage VB1.

An input terminal of the inverter INT11 is coupled to the correspondingfirst signal line 121. A first terminal of the transistor M13(corresponding to a first terminal of the first switch) is coupled to acorresponding second signal line 123, a control terminal of thetransistor M13 (corresponding to a control terminal of the first switch)receives the first line bias voltage VB1, a second terminal of thetransistor M13 (corresponding to a second terminal of the first switch)is coupled to a first terminal of the transistor M14 (corresponding to afirst terminal of the second switch). A control terminal of thetransistor M14 (corresponding to a control terminal of the secondswitch) is coupled to an output terminal of the inverter IN11, and asecond terminal of the transistor M14 (corresponding to a secondterminal of the second switch) receives a ground voltage.

TABLE 1 Working Status VB1 VC1 VC2 VL1 Operating Floating Read GroundReceived Mode State Voltage Voltage Voltage First Double Single SingleRead Setting Programming Programming Programming Voltage Mode VoltageVoltage Voltage Second Ground Single Single Read Setting VoltageProgramming Programming Voltage Mode Voltage Voltage

As shown in Table 1, the first control unit CU1 is roughly divided intoan operating mode and a setting mode (i.e., a first setting mode and asecond setting mode), wherein the first control unit CU1 is generallyoperated in the operating mode, and the setting mode is used to set orreset the resistive memories RX11 and RX12. Furthermore, in theoperating mode, the first line bias voltage VB1 is in a floating state,that is, the first line bias voltage VB1 is not supplied to the controlterminal of the transistor M13. Therefore, a voltage level of thecontrol terminal of the transistor M13 is not affected by the first linebias voltage VB1. The first control voltage VC1 is at a normal logiclevel and used as a read voltage of the bit information (impedancevalue) of the resistive memories RX11 and RX12; the second controlvoltage VC2 is the ground voltage. A line voltage VL1 changes with areceived voltage.

In the setting mode for setting the resistive memories RX11 and RX12(i.e., the first setting mode), the first line bias voltage VB1 is adouble programming voltage, that is, the first line bias voltage VB1 istwo times of the set voltage for programming the resistive memory RX11and RX12. The first control voltage VC1 and the second control voltageVC2 are single programming voltages. After that, each of the resistivememories RX11 and RX12 stores a logic bit “1”, that is, each of theresistive memory RX11 and RX12 has low impedance. Then, in the operatingmode, the voltage level of the control terminal of the transistor M13and the control terminal of the translator M14 are dependent on thelogic level (voltage level) of the line voltage VL1 of the first signalline 121, that is, after the first setting mode, a voltage level of thecorresponding second signal line 123 is dependent on a voltage level ofthe corresponding first signal line 121.

In the setting mode for resetting the resistive memories RX11 and RX12(i.e., the second setting mode), the first line bias voltage VB1 is theground voltage, and the first control voltage VC1 and the second controlvoltage VC2 are single programming voltages. After that, each of theresistive memories RX11 and RX12 stores the logic bit “0”, that is, eachof the resistive memories RX11 and RX12 has high impedance. Then, in theoperating mode, the voltage level of the control terminal of thetransistor M13 and the control terminal of the transistor M14 isindependent of the logic level (voltage level) of the line voltage VL1of the first signal line 121, that is, after the second setting mode,the voltage level of the corresponding second signal line 123 isindependent of the voltage level of the corresponding first signal line121.

FIG. 3 is a schematic diagram of a circuit of a first control unitaccording to an embodiment of the invention. Please refer to FIG. 1 andFIG. 3, wherein the same or similar reference numerals are used for thesame or similar parts. In this embodiment, each of the first controlunits CU1 includes a resistive memory RX21 (corresponding to the firstresistive memory) and an inverter INT21 (corresponding to the secondinverter), wherein the resistive memory RX21 includes a transistor M21and an impedance element R21.

An input terminal of the inverter INT21 is coupled to the correspondingfirst signal line 121. A first terminal of the transistor M21(corresponding to the first terminal of the first resistive memory)receives a third control voltage VC3, and a control terminal of thetransistor M21 (corresponding to the control terminal of the firstresistive memory) is coupled to an output terminal of the inverterINT21, and a second terminal of the transistor M21 is coupled to ananode of the impedance element R21. A cathode of the impedance elementR21 (corresponding to the second terminal of the first resistive memory)is coupled to the corresponding second signal line 123.

TABLE 2 Working Status VB2 VC3 VL1 Operating Floating Ground ReceivedMode Status Voltage Voltage First Single Ground Ground SettingProgramming Voltage Voltage Mode Voltage Second Ground Single GroundSetting Voltage Programming Voltage Mode Voltage

As shown in Table 2, the working modes of the first control unit CU1 areroughly divided into the operating mode and the setting mode (forexample, the first setting mode and the second setting mode), whereinthe first control unit CU1 is generally operated in the operating mode,and the setting mode is used to set or reset the resistive memory RX21.Furthermore, in the operating mode, a second line bias voltage VB2 is inthe floating state, that is, the second line bias voltage VB2 is notprovided to the corresponding second signal line 123. The third controlvoltage VC3 is the ground voltage. A voltage level of the first signalline 121 (i.e., the line voltage VL1) changes with the received voltage.

In the setting mode for setting the resistive memory RX21 (i.e., thefirst setting mode), the second line bias voltage VB2 is supplied to thecorresponding second signal line 123 and is the single programmingvoltage, that is, the set voltage for programming the resistive memoryRX21. The third control voltage VC3 is the ground voltage, and the linevoltage VL1 is the ground voltage. Thereafter, the resistive memory RX21stores the logic bit “1”, that is, the resistive memory RX21 has lowimpedance. Then, in the operating mode, the voltage level of thecorresponding second signal line 123 is dependent on a conduction stateof the transistor M21, that is, after the first setting mode, thevoltage level of the corresponding second signal line 123 is dependenton the line voltage VL1.

In the setting mode for resetting the resistive memory RX21 (i.e., thesecond setting mode), the second line bias voltage VB2 is supplied tothe corresponding second signal line 123 and is the ground voltage, thethird control voltage VC3 is the single programming voltage, and theline voltage VL1 is the ground voltage. Thereafter, the resistive memoryRX21 stores the logic bit “0”, that is, the resistive memory RX21 hashigh impedance. Then, in the operating mode, the voltage level of thecorresponding second signal line 123 is independent of the conductionstate of the transistor M21, that is, after the second setting mode, thevoltage level of the corresponding second signal line 123 is independentof the line voltage VL1.

FIG. 4 is a schematic diagram of a circuit of a second control unitaccording to an embodiment of the invention. Please refer to FIG. 1 andFIG. 4, wherein same or similar reference numerals are used for same orsimilar parts. In this embodiment, each of the second control units CU2includes a resistive memory RX31 (corresponding to the second resistivememory), wherein the resistive memory RX31 includes a transistor M31 andan impedance element R31. A first terminal of the transistor M31(corresponding to the first terminal of the second resistive memory)receives a fourth control voltage VC4, and a control terminal of thetransistor M31 (corresponding to a control terminal of the secondresistive memory) is coupled to the corresponding a third signal line131, and a second terminal of the transistor M31 is coupled to an anodeof the impedance element R31. A cathode of the impedance element R31(corresponding to a second terminal of the second resistive memory) iscoupled to a corresponding fourth signal line 133.

TABLE 3 Working Status VB3 VC4 VL2 Operating Floating Ground ReceivedMode State Voltage Voltage First Single Ground Read Setting ProgrammingVoltage Voltage Mode Voltage Second Ground Single Read Setting VoltageProgramming Voltage Mode Voltage

As shown in Table 3, the working modes of the second control unit CU2can be roughly divided into the operating mode and the setting mode (forexample, the first setting mode and the second setting mode), whereinthe second control unit CU2 is generally operated in the operating mode,and the setting mode is used to set or reset the resistive memory RX31.Furthermore, in the operating mode, a third line bias voltage VB3 is inthe floating state, that is, the third line bias voltage VB3 is notprovided to the corresponding fourth signal line 133; the fourth controlvoltage VC4 is the ground voltage; a voltage level of the correspondingthird signal line 131 (i.e., a line voltage VL2) changes with thereceived voltage.

In the setting mode for setting the resistive memory RX31 (that is, thefirst setting mode), the third line bias voltage VB3 is supplied to thecorresponding fourth signal line 133 and is the single programmingvoltage, that is, the set voltage for programming the resistive memoryRX31; the fourth control voltage VC4 is the ground voltage; and the linevoltage VL2 is the read voltage. Thereafter, the resistive memory RX31stores the logic bit “1”, that is, the resistive memory RX31 has lowimpedance. Then, in the operating mode, a voltage level of thecorresponding fourth signal line 133 is dependent on a conduction stateof the transistor M31, that is, after the first setting mode, thevoltage level of the corresponding fourth signal line 133 is dependenton the line voltage VL2.

In the setting mode for resetting the resistive memory RX31 (i.e., thesecond setting mode), the third line bias voltage VB3 is supplied to thecorresponding fourth signal line 133 and is the ground voltage, and thefourth control voltage VC3 is the single programming voltage; the linevoltage VL2 is the read voltage. Thereafter, the resistive memory RX31stores the logic bit “0”, that is, the resistive memory RX31 has highimpedance. Then, in the operating mode, the voltage level of thecorresponding fourth signal line 133 is independent of the conductionstate of the transistor M31, that is, after the second setting mode, thevoltage level of the corresponding fourth signal line 133 is independentof the line voltage VL2.

In summary, the programmable array logic of the embodiment of theinvention can set the voltage levels of the first and second signallines by setting and resetting the first (and third) resistive memory.The relationship between the voltage levels of the third and fourthsignal lines can be set by setting and resetting the second resistivememory. Thereby, the flexibility and performance of the use can beimproved, and the hardware cost can be taken into consideration.

Although the present invention has been disclosed in the aboveembodiments, it is not intended to limit the invention, and thoseskilled in the art can make a few changes without departing from thespirit and scope of the invention. The scope of protection of thepresent invention is defined by the scope of the appended claims.

What is claimed is:
 1. A programmable array logic, comprising: aplurality of programmable AND gates; a plurality of first signal linesand a plurality of second signal lines, wherein the second signal linesare respectively coupled to input terminals of programmable AND gates; aplurality of first control units, respectively coupled to thecorresponding first signal line and the corresponding second signalline, wherein each of the first control units has at least one firstresistive memory, and the first resistive memory is configured topermanently isolate a first signal line coupled thereto from a secondsignal line coupled thereto, and set a relationship between a voltagelevel of the corresponding first signal line and a voltage level of thecorresponding second signal line; a plurality of programmable OR gates;a plurality of third signal lines and a plurality of fourth signallines, wherein the third signal lines are respectively coupled to outputterminals of the programmable AND gates, and the fourth signal lines arerespectively coupled to input terminals of programmable OR gates; and aplurality of second control units, respectively coupled to thecorresponding third signal line and the corresponding fourth signalline, wherein each of the second control units has a second resistivememory, and the second resistive memory is configured to permanentlyisolate a third signal line coupled thereto from a fourth signal linecoupled thereto, and set a relationship between a voltage level of thecorresponding third signal line and a voltage level of the correspondingfourth signal line.
 2. The programmable array logic according to claim1, wherein each of the first control units comprises: the firstresistive memory, having a first terminal receiving a first controlvoltage, a control terminal coupled to the corresponding first signalline, and a second terminal receiving a first line bias voltage; a thirdresistive memory, having a first terminal receiving a second controlvoltage, a control terminal coupled to the corresponding first signalline, and a second terminal receiving the first line bias voltage; afirst inverter, having an input terminal coupling to the correspondingfirst signal line and an output terminal; a first switch, having a firstterminal coupled to the corresponding second signal line, a controlterminal receiving the first line bias voltage, and a second terminal;and a second switch, having a first terminal coupled to the secondterminal of the first switch, a control terminal coupled to the outputterminal of the first inverter, and a second terminal receiving a groundvoltage.
 3. The programmable array logic according to claim 2, whereinin an operating mode, the first line bias voltage is a floating state,and the first control voltage is a read voltage, and the second controlvoltage is the ground voltage, in a first setting mode, the first linebias voltage is a double programming voltage, and the first controlvoltage and the second control voltage are a single programming voltage,and in a second setting mode, the first line bias voltage is the groundvoltage, and the first control voltage and the second control voltageare the single programming voltage.
 4. The programmable array logicaccording to claim 3, wherein after the first setting mode, a voltagelevel of the corresponding second signal line is dependent on a voltagelevel of the corresponding first signal line, and after the secondsetting mode, the voltage level of the corresponding second signal lineis independent of the voltage level of the corresponding first signalline.
 5. The programmable array logic according to claim 1, wherein eachof the first control units comprises: the first resistive memory havinga first terminal receiving a third control voltage, a control terminal,and a second terminal coupled to the corresponding second signal line;and a second inverter having an input coupled to the corresponding firstsignal line, and an output coupled to the control terminal of the firstresistive memory.
 6. The programmable array logic according to claim 5,wherein in an operating mode, the corresponding second signal line doesnot receive a second line bias voltage, and the third control voltage isa ground voltage, in a first setting mode, the second line bias voltageis a programming voltage and is applied to the corresponding secondsignal line, the third control voltage is the ground voltage, and avoltage level of the corresponding first signal line is the groundvoltage, and in a second setting mode, the second line bias voltage isthe ground voltage and is applied to the corresponding second signalline, the third control voltage is the programming voltage, and thevoltage level of the corresponding first signal line is the groundvoltage.
 7. The programmable array logic according to claim 6, whereinafter the first setting mode, a voltage level of the correspondingsecond signal line is dependent on the voltage level of thecorresponding first signal line, after the second setting mode, thevoltage level of the corresponding second signal line is independent ofthe voltage level of the corresponding first signal line.
 8. Theprogrammable array logic according to claim 1, wherein each of thesecond control units comprises: the second resistive memory having afirst terminal receiving a fourth control voltage, a control terminalcoupled to the corresponding third signal line, and a second terminalcoupled to the corresponding fourth signal line.
 9. The programmablearray logic according to claim 8, wherein in an operating mode, thecorresponding fourth signal line does not receive a third line biasvoltage, and the fourth control voltage is a ground voltage, in a firstsetting mode, the third line bias voltage is a programming voltage andis applied to a corresponding fourth signal line, the fourth controlvoltage is the ground voltage, and the voltage level of thecorresponding third signal line is a read voltage, and in a secondsetting mode, the third line bias voltage is the ground voltage and isapplied to the corresponding fourth signal line, the fourth controlvoltage is the programming voltage, and the voltage level of thecorresponding third signal line is the read voltage.
 10. Theprogrammable array logic according to claim 1, further comprising aninverting/non-inverting block coupled to the first signal lines, whereinthe first signal lines receive a plurality of input bits and a pluralityof inverted input bits, the programmable OR gates provide a plurality ofoutput bits, and the inverting/non-inverting block receives the inputbits to provide the input bits and the inverted input bits, wherein theinverting/non-inverting block comprises a plurality of inverters,respectively receiving corresponding input bits to provide correspondinginverted input bits.
 11. The programmable array logic according to claim1, wherein the first resistive memory comprises a first impedanceelement, a cathode of the first impedance element is coupled to thecorresponding second signal line, and the first resistive memory isconfigured to set the relationship between the voltage level of thefirst signal line which is coupled to the first resistive memory and thevoltage level of the second signal line which is coupled to the firstresistive memory, wherein the second resistive memory comprises a secondimpedance element, a cathode of the second impedance element is coupledto the corresponding fourth signal line, and the second resistive memoryis configured to set the relationship between the voltage level of thethird signal line which is coupled to the second resistive memory andthe voltage level of the fourth signal line which is coupled to thesecond resistive memory.